Moore's Lobby: Where engineers talk all about circuits

Sensors are shrinking. They are moving into places we never thought possible. In this episode of Moore's Lobby, host Daniel Bogdanoff sits down with Ted Karlin from Infineon. They discuss how 60 GHz radar is changing the electronics landscape. From smart homes to consumer laptops, radar is replacing traditional cameras. Learn why this high-frequency technology is the next big step in hardware design.
Breaking Down 60 GHz Pure CMOS Radar
Traditional radar systems often rely on BiCMOS technology. However, Infineon is pushing the boundaries. They are bringing a 60 GHz radar device to the market built on a pure CMOS process. This transition provides major benefits for modern system design. It offers higher transmit efficiency, longer range, and a wider field of view. Most importantly, it does this at a much lower power.
Pure CMOS also enables massive on-chip processing. This allows the radar sensor to run autonomously. It can perform "wake on motion" tasks while the host MCU stays asleep. This saves valuable battery life.
Antenna-in-Package (AIP): This technology integrates antennas directly into the chip packaging, eliminating complex PCB RF layout requirements.
Pure CMOS Process: Shifting away from BiCMOS allows engineers to shrink silicon nodes, leading to smaller, more power-efficient devices.
Wake on Motion: The radar chip senses movement and processes data autonomously, keeping the host processor asleep to save power.
Integrating high-frequency RF components into a compact package is a major challenge. Packaging engineers must isolate multiple die and mitigate mechanical stress. For MEMS and radar, improper packaging can lead to false readings. If designed correctly, 60 GHz radar can transmit directly through non-conductive enclosures. This allows for completely sealed, seamless industrial designs.

The semiconductor landscape is changing faster than ever. Chips now power everything from AI to advanced automotive systems. At the heart of this rapid revolution is semiconductor intellectual property (IP).
In this episode, Daniel Bogdanoff sits down with John Koeter of Synopsys. They explore how pre-verified silicon blocks accelerate chip design. They also discuss the massive shift toward multi-die systems and the future role of AI in engineering.
 
Accelerating Chip Design with Pre-Verified IP and Multi-Die Architectures
As Moore's law slows down, chip designers face extreme physical challenges. Designing a complex system-on-chip (SoC) from scratch is no longer viable. Companies rely on proven IP blocks to speed up time-to-market and ensure silicon success.
Today, the industry is transitioning to multi-die systems. Instead of one massive chip, designers stack multiple specialized chiplets in advanced packages. This transition introduces complex thermal and power challenges that require highly accurate modeling.
System on a Chip (SoC): An integrated circuit that combines all necessary electronic circuits and parts on a single chip.

Multi-Die Systems (Chiplets): An architecture where multiple specialized dies are combined in a single package to maximize performance.

Model to Hardware Correlation (MHC): The practice of ensuring pre-silicon simulation models accurately predict real-world post-silicon behaviors.

Managing thermal distribution is the biggest hurdle in 3D IC design. Stacking chips creates intense hotspots. These hotspots can crack or delaminate packages if unmanaged. Engineers must use advanced simulation tools to model these thermal characteristics early in the design cycle.

Joaquin Torrecilla began his engineering career programming a Sinclair Spectrum in Basic and Assembler. He later tested some of the industry's very first commercial Bluetooth solutions. Today, he remains at the forefront of RF and protocol testing. In this episode, Joaquin shares key insights from his 20 years with the 3GPP RAN Plenary. He also discusses the complex balance required to create and certify global wireless testing standards.
The conversation dives deep into the game-changing capabilities of 5G Advanced. Joaquin breaks down the impact of:
Network Slicing: Customizing virtual channels for specific industry needs.
Time-Sensitive Networking (TSN): Keeping strict synchronization across wired and wireless systems.
Non-Terrestrial Networks (NTNs): Connecting standard devices directly to space.
Joaquin explains how fast-moving low Earth orbit (LEO) satellites manage continuous handovers overhead. We also learn how these satellites use high-precision laser links to talk to each other in orbit. Finally, he explains RedCap (Reduced Capacity) 5G. This technology acts as a cost-optimized, low-power bridge for smartwatches and IoT devices.
Looking to the future, Joaquin discusses the early stages of 6G. This next generation of wireless will be AI-native from day one. Its architecture will automatically optimize network layers and manage massive amounts of test data.
Joaquin now leads software transformation at Keysight. This background allows him to highlight how modern networks are moving away from proprietary hardware boxes and shifting to virtualized software stacks. To wrap up, Joaquin offers great advice for younger engineers. He explains why the test and measurement industry provides unmatched, system-level knowledge.

In this insightful interview, embedded computing pioneer Christian Eder sits down with host Daniel Bogdanoff to explore the past, present, and future of modular systems design. As a co-founder of congatec, Christian draws on over 30 years of industry experience to highlight how Computer-on-Modules (COMS) have transformed modern electronics.
Christian discusses the strategic decisions that fueled congatec's growth into a leading board manufacturer and outlines why standardizing technology benefits the entire ecosystem. He details the development and roll-out of critical open standards, particularly PICMG's COM-HPC. This standard addresses the ever-growing demand for high-performance edge computing, massive memory throughput, and server-level capabilities in compact footprints.
The conversation highlights several key technical insights and future directions, including:
The Power of Open Standards: How collaborative standards lower design complexity, prevent vendor lock-in, and accelerate time-to-market.

The Shift to the Edge: Managing massive data requirements and the rise of edge AI processing through next-generation modular form factors.

COM-HPC vs. COM Express: Understanding the performance leaps, pinouts, and architectural shifts required for high-speed PCIe Gen 5 and Gen 6 interfaces.

Building a Tech Giant: The entrepreneurial lessons learned from co-founding congatec and driving global standards.

Drawing on his experience, Christian offers unique insights into why the smartest hardware strategies start with a modular mindset.

In this fascinating interview, Sergiy Nesterenko details the journey that ultimately drove him to solve a critical bottleneck in hardware engineering: the manual, slow process of printed circuit board (PCB) layout.
In his discussion with our Moore's Lobby host, Daniel Bogdanoff, Sergiy shares engaging anecdotes from his early career, including a SpaceX internship where he was assigned to literally watch paint dry. He also describes his first attempt at PCB layout at SpaceX, where a power switch board caught fire in his hands. This experience fueled his desire to bring robust automation to the PCB design field.
Sergiy explains why traditional auto-routers have failed to gain widespread adoption for sixty years. He then explains how Quilter solves this by leveraging reinforcement learning and computational physics.
They discuss several major technical insights and future directions, including:
-The software compiler analogy. 
-Physics-based automation.
-Tackling complex boards. 
-His 10-year vision.